Senior Chip Timing & Implementation Engineer (hybrid)
Renesas
Duluth, Georgia, US
About the Role
A leading semiconductor solutions provider is seeking an experienced engineer skilled in full chip and block timing analysis. The candidate will develop and enhance methodologies related to synthesis and verification while collaborating closely with multi-functional teams. Ideal candidates have a strong digital design foundation and experience with various tools necessary for timing challenges. This position promotes a flexible hybrid work model, fostering team innovation and support. #J-18808-Ljbffr
Required Skills
timing analysis
synthesis
verification
digital design
tool proficiency
Keywords
chip timing
implementation
hybrid
semiconductor
timing analysis
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